Parallel NAND system power and energy calculator

Micron products are warranted only to meet Micron’s data sheet specifications. This tool, Micron products, programs and specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Additional verification of calculation outputs is recommended to ensure accuracy.

Approximating NAND average power/energy consumption for a system is a useful exercise to help determine NAND device power consumption’s role in a system’s power/energy budget and how to potential optimize that budget for NAND operations. This tool provides an estimate of NAND current/power/energy consumption per host channel and system NAND power/energy consumption for a NAND Read-Program-Erase-Idle-Standby workload.

The audience for this calculator is a user looking to approximate NAND power/energy consumption who understands the NAND devices used, type of NAND operations used, their respective current (Icc) specifications, number of bytes outputted/inputted, and their respective NAND array busy times (e.g., tR, tPROG, tBERS). The user of this calculator is expected to know the physical and operational characteristics of the system such as (but not limited to) NAND host data input/output interface speed, system parallel use of the NAND LUNs/die, voltage supply levels to the NAND, NAND Read-Program-Erase-Idle-Standby workloads, capacitance of board traces - controller DQ bus - and other physical system elements.

Enter a value for each item

  • Parallel NAND device with DQ[7:0] or DQ[15:0] bus being used by the host system (1 = DQ[7:0] NAND device used, 2 = DQ[15:0] NAND device used)
    This value should be either 1 or 2

  • Number of NAND DQ[7:0] or NAND DQ[15:0] host channels

  • Number of NAND LUNs/die per host channel

  • Number of NAND CE# signal per host channel (assumed to be evenly distributed by # of NAND LUNs/die per host channel)

  • Host NAND interface speed in MT/s (e.g. 50 for 50MT/s, 800 for 800MT/s, etc.)

  • Capacitive loading of host system per NAND DQ[7:0] or NAND DQ[15:0] channel in pF not including NAND devices

  • Host system supplied NAND Vcc in Volts

  • Host system supplied NAND Vccq in Volts

  • Host system supplied NAND Vpp in Volts (if used)

  • Number of NAND LUNs/die per host NAND DQ[7:0] or NAND DQ[15:0] channel are busy (SR5 = 0) with the most used Read operation at the same time
    This value should not be greater than the value used in the 'Number of NAND LUNs/die per host channel' row

  • Number of bytes outputted associated with the most used Read operation. If using multi-plane operations, include all bytes outputted from all planes.

  • Number of NAND LUNs/die per host NAND DQ[7:0] or NAND DQ[15:0] channel are busy (SR5 = 0) with the 2nd most used Read operation at the same time
    This value should not be greater than the value used in the 'Number of NAND LUNs/die per host channel' row

  • Number of bytes ouputted associated with the 2nd most used Read operation. If using multi-plane operations, include all bytes outputted from all planes.

  • Number of NAND LUNs/die per host NAND DQ[7:0] or NAND DQ[15:0] channel are busy (SR5 = 0) with the most used Program operation at the same time
    This value should not be greater than the value used in the 'Number of NAND LUNs/die per host channel' row

  • Number of bytes inputted associated with the most used Program operation. If using multi-plane operations, include all bytes inputted for all planes.

  • Number of NAND LUNs/die per host NAND DQ[7:0] or NAND DQ[15:0] channel that are busy (SR5 = 0) with the most used Erase operation at the same time
    This value should not be greater than the value used in the 'Number of NAND LUNs/die per host channel' row

  • NAND mode of operation used by the host system (1 = Async mode, 2 = NV-DDR/NV-DDR2/NV-DDR3 mode, 3 = NV-LPDDR4 mode)
    This value should be 1, 2, or 3

  • Capacitance of the NAND package DQ[7:0] or DQ[15:0] channel in pF

  • Number of NAND package DQ[7:0] or DQ[15:0] channels shorted/shared per host NAND DQ[7:0] or DQ[15:0] channel

  • NAND array Read current for most used Read operation (e.g. NAND Icc1 specification) in mA

  • NAND array Read time (e.g., tR, tR_IWL, etc.) for most used Read operation in microseconds (µs)

  • NAND array Read current for 2nd most used Read operation (e.g. NAND Icc1 specification) in mA

  • NAND array Read time (e.g., tR, tR_IWL, etc.) for 2nd most used Read operations in microseconds (µs)

  • NAND Program current for most used Program operation (e.g. NAND Icc2 specification) in mA

  • NAND Program time (e.g., tPROG) for most used Program operation in microseconds (µs)

  • NAND Erase current for most used Erase operation (e.g. NAND Icc3 specificaiton) in mA

  • NAND Erase time (e.g., tBERS) for most used Erase operation in milliseconds (ms)

  • NAND Vpp current for most used Read operations (e.g. NAND IPPA1 specification, if used) in mA

  • NAND Vpp current for 2nd most used Read operations (e.g. NAND IPPA1 specification, if used) in mA

  • NAND Vpp current for Program operations (e.g. NAND IPPA2 specification, if used) in mA

  • NAND Vpp current for Erase operations (e.g. NAND IPPA3 specification, if used) in mA

  • NAND standby current (e.g. NAND Isb and Isbq specification) in µA

  • NAND Idle current (e.g. Icc5 and Iccq5 specifications) in mA

  • NAND data output current at the NAND interface speed being used (e.g. NAND Icc4r and Iccq4r specificaiton) in mA

  • NAND data input current at the NAND interface speed being used (e.g. NAND Icc4w and Iccq4w specification) in mA

  • NAND array Read current on Vccq rail (e.g. NAND Iccq1 specification) in mA

  • NAND array Program current on Vccq rail (e.g. NAND Iccq2 specification) in mA

  • NAND array Erase current on Vccq rail (e.g. NAND Iccq3 specification) in mA

Results

System Workload breakout per host NAND channel

  • Most used Read Operation %

  • Most used Program Operation %

  • % of time a NAND die is in Idle state

  • 2nd most used Read Operation %

  • Most used Erase Operation %

  • % of time a NAND die is in Standby state

  • Total NAND Power per host channel (in W)

  • Total NAND Energy per host channel (in mJ)

    Energy calculations only take into account Read, Program, and Erase inputs

  • Total NAND Power for all host channels (in W)

  • Total NAND Energy for all host channels (in mJ)

    Energy calculations only take into account Read, Program, and Erase inputs.

Values for NAND LUNs/die busy with most used Read Operation

  • NAND system current per channel (in mA)

  • NAND system power per channel (in W)

  • NAND system energy per channel (in mJ)

  • NAND Vcc rail during NAND array operations

  • NAND Vccq rail during NAND array operations

  • NAND Vcc rail during data output

  • NAND Vccq rail during data output

Values for NAND LUNs/die busy with 2nd most used Read operation

  • NAND system current per channel (in mA)

  • NAND system power per channel (in W)

  • NAND system energy per channel (in mJ)

  • NAND Vcc rail during NAND array operations

  • NAND Vccq rail during NAND array operations

  • NAND Vcc rail during data output

  • NAND Vccq rail during data output

Values for NAND LUNs/die busy with most used Program

  • NAND system current per channel (in mA)

  • NAND system power per channel (in W)

  • NAND system energy per channel (in mJ)

  • NAND Vcc rail during NAND array operations

  • NAND Vccq rail during NAND array operations

  • NAND Vcc rail during data input

  • NAND Vccq rail during data input

Values for NAND LUNs/die busy with most used Erase operation

  • NAND system current per channel (in mA)

  • NAND system power per channel (in W)

  • NAND system energy per channel (in mJ)

  • NAND Vcc rail during NAND array operations

  • NAND Vccq rail during NAND array operations

  • NAND Vpp rail during array operations (if used)

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